Testbenches in Verilog

 ⚙️ 1. Behavioral Modeling

Behavioral modeling describes what the circuit does, not how it’s built.

It focuses on the function or logic using high-level statements like if, case, and always blocks.

🔸 Example – Behavioral 2-bit Adder

module adder_behavioral(input [1:0] A, B, output reg [2:0] SUM);

  always @(*) begin

    SUM = A + B;   // Describes the behavior

  end

endmodule

✅ Advantages:

Easier and faster to write

Good for algorithmic or complex designs

Useful for simulation and verification

⚠️ Limitation:

Doesn’t show the internal hardware structure

🔩 2. Structural Modeling

Structural modeling describes how the circuit is built using gates and interconnections.

It focuses on the hardware components and how they’re connected.

🔸 Example – Structural 2-bit Adder

module half_adder(input A, B, output SUM, CARRY);

  xor(SUM, A, B);

  and(CARRY, A, B);

endmodule

module full_adder(input A, B, Cin, output SUM, Cout);

  wire s1, c1, c2;

  half_adder h1(A, B, s1, c1);

  half_adder h2(s1, Cin, SUM, c2);

  or(Cout, c1, c2);

endmodule

✅ Advantages:

Shows exact hardware connections

Great for gate-level simulation or FPGA design

⚠️ Limitation:

Time-consuming for large circuits

🧠 Summary Table

Feature Behavioral Modeling Structural Modeling

Focus Functionality Hardware structure

Description High-level (algorithmic) Low-level (gates/modules)

Readability Easy Complex for large designs

Usage Simulation, testing Hardware implementation